1. Field of the Invention
This invention relates to the measurement of relative frequencies between and more particularly, to the detection of a frequency difference above an allowable threshold.
2. Background of the Invention
In many high-speed communications applications, such as the Synchronous Optical Network (SONET) communication standard, a transceiver receives an incoming data signal that contains an embedded clock signal. The embedded clock signal in the incoming signal corresponds to a reference frequency, which is a master clock for the system. A clock recovery unit (CRU), or a clock and data recovery (CDR) circuit, recovers the embedded clock signal from the incoming data signal. The CRU uses this recovered clock signal to phase-lock a local oscillator to the edges of the incoming data signal, wherein the local oscillator is synchronized and trained to the frequency of the recovered clock signal. The local oscillator is then used to generate a local clock signal to process and re-time the data received in the incoming signal.
Because the local oscillator""s clock signal is used to retrieve the data from the incoming signal, it is important that the local oscillator be very close to a multiple of the reference frequency. Otherwise, if the frequency difference between the local oscillator and a multiple of the reference deviates by more than a tolerable amount, the system may not properly decode the data from the incoming signal. Therefore, it is desirable to measure the frequency of the local oscillator relative to the reference signal to determine whether the locally-generated clock signal is close enough in frequency to the reference signal. This measurement is used to perform lock detection. If the local oscillator is not locked to the correct frequency, the system may have to correct the problem, such as by retraining the local oscillator.
FIG. 1 shows a simplified block diagram of one type of CRU for performing recovery, re-timing, and lock detection of an incoming data signal. This CRU is based on a phase-locked loop (PLL) that contains a digital frequency and phase detector (DFPD) 105, known as a digital quadri-correlator, which can extract the information from the incoming data without requiring an external clock reference for frequency acquisition. The incoming data is compared against an internal voltage controlled oscillator (VCO) in the DFPD 105. Its output is differentially filtered by filter 110 and applied to the oscillator 115. The data is re-timed by a D flip-flop 125 using the inverted in-phase VCO clock output.
A lock detector 130 compares a reference input, REF, against the VCO 115 (e.g., divided by 16). The lock detector 130 determines whether the frequency difference between the local oscillator 115 and the reference signal is within a prescribed tolerance. The lock detector 130 will alert the circuit to such a problem so that the circuit can take appropriate action. For example, if the relative error between the two signals"" frequencies is too large, the CRU can be commanded to directly train its oscillator to a multiple of the reference frequency.
FIG. 2 shows a proposed lock detector 130, which works as a relative frequency measuring system. This lock detector 130 determines if an optional reference and the internally divided-down VCO 115 are different by more than a preset percentage. The basis of its operation is the generation of a beat frequency between the two inputs by the use of a pair of flip-flops 205,210. This beat signal enables a counter 215 that counts either the reference or the divided-down VCO 115. If the two inputs are close in frequency, then a high count will occur during the beat signal high state. Then the counter 215 will xe2x80x9coverflowxe2x80x9d and disarm a trip point set by the beginning of the beat waveform by an S-R flip-flop 220. Accordingly, this sets a xe2x80x9clockedxe2x80x9d signal that indicates whether the two inputs have frequencies within the preset percentage tolerance.
It has been found, however, that the lock detector 130 of FIG. 2 is unreliable due to minor deviations of the input signals, specifically variations in period frequency displacements from the signals"" ideal locations. This phenomenon is commonly called jitter. When jittery input signals are combined to form a beat signal, these period frequency deviations will cause the beat signal to xe2x80x9cchatterxe2x80x9d as one input signal overtakes the other. Chatter is characterized by a signal that beats with hesitation (i.e., goes up and down before settling in a final value) at the rising and/or falling edges of the signal. Because the beat signal is used to enable the counter 215 and set the TRIP bit (which ultimately sets the LOCKED bit), any chatter in the beat signal can cause the system to not operate correctly. For example, the chatter can prematurely reset the counter 215, or it can fail to keep the TRIP and LOCKED bits at their appropriate high or low value.
Other conventional solutions for lock detection typically include at least twice as many components as the lock detector of FIG. 2 and are significantly more complex. In addition, such conventional solutions are not easily programmable. It is therefore desirable to develop a lock detector that will detect frequency differences between signals and produce a reliable lock detection signal, while avoiding the problems of conventional solutions.
A lock detector is described for detecting a difference between the frequencies of a first and a second input signal. The lock detector includes first and second beat generators configured to generate corresponding beat signals based on the first and second input signals. The second beat signal is phase shifted relative to the first beat signal. A chatter elimination module combines the two chattery beat signals to produce a third corresponding beat signal that is substantially free of chatter. Using this clean beat signal and either of the input signals, a lock detection module produces a lock detection signal, which indicates whether the difference between the frequencies of the first and second input signals is within a prescribed tolerance. In one embodiment of the invention, the lock detector is implemented using various arrangements of flip-flops, counters, and other standard logic and circuit components.
The present invention has many advantages over conventional systems and methods. For example, the present invention uses fewer components, which saves power, requires less area, and is easy to implement. Moreover, the use of a counter or similar components in the lock detection module allows the system to be easily programmed for different tolerances in frequency difference. The system is also advantageously not affected by the relative sign of the frequency measurement (i.e., which input""s frequency is higher than the other). Lastly, the system avoids the problems of chatter by producing a clean beat signal and using that clean signal to control the system.